A Chaotic Oscillator Cell in Subthreshold Cmos for Spatio-temporal Simulation

This paper reports on the design and experimental results of a subthreshold-CMOS chaotic oscillator suitable for single-chip VLSI synthesis of coupled maps generating spatio-temporal chaos. The circuit is autonomous and generates chaotic signals in three state variables in a manner analogous to a Chua circuit. Previous CMOS oscillators operate above threshold and utilize current over two orders of magnitude larger than a subthreshold design. By using existing nonlinear building blocks, the current design permits simple adjustment of bifurcation parameters for investigation of complex phenomena not present in a piecewise linear model. Since this design incorporates all necessary elements on chip, its combination of reduced size and exible nonlinearities make it suitable for a single-chip VLSI synthesis of complex circuits making use of chaotic signals, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.